# UART capture peripheral in RTL

Unique Acevedo — Planning brief

**Planned · not started. These are proposed requirements and tests, not achieved results.**

My coursework includes digital logic and computer architecture. I want to develop an original UART receive block that makes timing, buffering, and error handling visible in both the RTL and the tests. The first milestone is a written interface specification; no implementation or simulation results exist yet.

## Make timing assumptions explicit

Parameterize clock and baud settings. Document input synchronization, start-bit qualification, sample positions, and the acceptable timing mismatch before building the state machine.

## Define behavior at the boundaries

Preserve unread data when the FIFO is full, drop the newest incoming byte, and report overflow. Specify empty reads, simultaneous push/pop, error clearing, and reset during a frame. Framing errors and buffer overflow need separate reporting.

## Verify against an independent model

Use a Python transmitter and scoreboard instead of deriving the expected result from the receiver’s internal state. Keep reproducible seeds and waveforms when a test fails.

## Separate simulation, synthesis, and hardware

Archive simulator commands, tool versions, and a synthesis report for a named target. An FPGA demonstration would be a later milestone with its own clock, pin, and hardware checks.

## How I plan to test it

- [ ] Recover all 256 byte values and back-to-back frames without unintended loss or reordering.
- [ ] Vary start phase and transmitter timing; state the baud-error range actually tested.
- [ ] Inject a low stop bit, a false start, prolonged low input, and reset during reception.
- [ ] Exercise FIFO full/empty boundaries and verify exactly which data is retained or discarded.
- [ ] Run reproducible randomized traffic against the independent scoreboard and archive failures.
- [ ] Synthesize for a named target and preserve scripts and resource reports.

## Next artifacts

- Write the register map, timing assumptions, and failure policies.
- Implement the receiver and independent tests in small, reviewable steps.
- Publish RTL, test commands, waveforms, and synthesis results only after they exist.

## Technical references

- [Microchip: UART frame format](https://onlinedocs.microchip.com/oxy/GUID-173AD72D-41FE-4760-A93C-7078A02BD908-en-US-7.1.1/GUID-585072A2-2328-4EDD-B24F-E2E7672632B5.html)
- [cocotb: Writing testbenches](https://docs.cocotb.org/en/stable/writing_testbenches.html)
- [Yosys: Synthesis example](https://yosyshq.readthedocs.io/projects/yosys/en/stable/getting_started/example_synth.html)