Make timing assumptions explicit
Parameterize clock and baud settings. Document input synchronization, start-bit qualification, sample positions, and the acceptable timing mismatch before building the state machine.
Entry 06 / Digital design
UART capture peripheral in RTL.
Receiving a byte is only the beginning.
Planned · not startedPROPOSED ARCHITECTURE / UART
- 01RXSynchronize
- 02SAMPLEQualify & decode
- 03FIFOBuffer & flag
- 04READData & status
DEFINE → IMPLEMENT → VERIFY → DOCUMENT
01 / The work
Receiving a byte is only the beginning.
My coursework includes digital logic and computer architecture. I want to develop an original UART receive block that makes timing, buffering, and error handling visible in both the RTL and the tests. The first milestone is a written interface specification; no implementation or simulation results exist yet.
Define behavior at the boundaries
Preserve unread data when the FIFO is full, drop the newest incoming byte, and report overflow. Specify empty reads, simultaneous push/pop, error clearing, and reset during a frame. Framing errors and buffer overflow need separate reporting.
Verify against an independent model
Use a Python transmitter and scoreboard instead of deriving the expected result from the receiver’s internal state. Keep reproducible seeds and waveforms when a test fails.
Separate simulation, synthesis, and hardware
Archive simulator commands, tool versions, and a synthesis report for a named target. An FPGA demonstration would be a later milestone with its own clock, pin, and hardware checks.
Proposed validation / no tests run yet
How I plan to test it.
- 01
Recover all 256 byte values and back-to-back frames without unintended loss or reordering.
- 02
Vary start phase and transmitter timing; state the baud-error range actually tested.
- 03
Inject a low stop bit, a false start, prolonged low input, and reset during reception.
- 04
Exercise FIFO full/empty boundaries and verify exactly which data is retained or discarded.
- 05
Run reproducible randomized traffic against the independent scoreboard and archive failures.
- 06
Synthesize for a named target and preserve scripts and resource reports.
Technical references
Microchip: UART frame formatcocotb: Writing testbenchesYosys: Synthesis example